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3. Design Rules and Procedures
This chapter discusses the following topics:
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“DSP Builder Naming Conventions”
“Using a MATLAB Variable”
“Fixed-Point Notation”
“Bit Width Design Rule”
“Frequency Design Rules”
“Timing Semantics Between Simulink and HDL Simulation”
“Signal Compiler and TestBench Blocks”
“Hierarchical Design”
“Goto and From Block Support”
“Create Black Box and HDL Import”
“Using a MATLAB Array or .hex File to Initialize a Block”
“Comparison Utility”
“Adding Comments to Blocks”
“Adding Quartus II Constraints”
“Displaying Port Data Types”
“Displaying the Pipeline Depth”
“Updating HDL Import Blocks”
“Analyzing the Hardware Resource Usage”
“Loading Additional ModelSim Commands”
“Making Quartus II Assignments to Block Entity Names”
DSP Builder Naming Conventions
DSP Builder generates VHDL files for simulation and synthesis. When there are
blocks or ports in your model that share the same VHDL name, they are given unique
names in the VHDL to avoid name clashes. However, clock and reset ports are never
renamed, and an error issues if they do not have unique names. Avoid name clashes
on other ports, to avoid renaming of the top-level ports in the VHDL.
All DSP Builder port names must comply with the following naming conventions:
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VHDL is not case sensitive. For example, the input port MyInput and MYINPUT is the
same VHDL entity.
Avoid using VHDL keywords for DSP Builder port names.
Do not use illegal characters. VHDL identifier names can contain only a - z, 0 - 9,
and underscore (_) characters.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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